In semiconductor device manufacturing, lithography is typically used to transfer a pattern for forming semiconductor features onto the semiconductor wafer for the formation of multi-layered structures to form integrated circuits. During a lithographic process, also commonly referred to as a photolithographic process, radiant energy having relatively small wavelengths such as ultraviolet light is passed through a mask, also referred to as a reticle, to expose a radiant energy sensitive material such as photoresist, also frequently referred to as resist, formed on the wafer process surface. The mask includes predetermined circuitry patterns having regions of attenuating and non-attenuating regions where the radiant energy intensity is modulated. For example, ultraviolet (UV) light passed through the mask onto the photoresist causes chemical reactions in the exposed portion of the photoresist, altering it properties. Upon development of the photoresist resist, exposed portions are removed in the case of a positive photoresist, and non-exposed portions are removed in the case of a negative photoresist.
As semiconductor device feature sizes have decreased to sizes smaller than the wavelength of light used in photolithographic processes, the reflection of light during the patterning process from layers underlying the photoresist layer cause the unintentional exposure of photoresist portions at a bottom portion of the photoresist layer thereby causing widening or undercutting of the pattern at the resist/wafer process surface interface. As a result, critical dimensions are compromised during a subsequent dry etching process.
Anti-reflectance coating (ARC) layers, also frequently referred to as dielectric anti-reflectance coatings (DARC), and bottom anti-reflectance coatings (BARC) are known in the semiconductor microelectronic IC fabrication process for reducing light reflections during a photolithographic exposure process. For example, a layer of material having a desired index of refraction and thickness is fabricated to reduce light reflections from the ARC layer surface and an underlying layer, for example an etching stop layer. For example, the dielectric layer may be tuned to produce index of refraction matching at the interface of the ARC layer and underlying layer. Several ARC formulations are known in the art, for example, including an ARC formed of silicon oxynitride (e.g., SixOyN), whose optical properties may be selected during a CVD formation process.
Frequently, photolithographic patterning processes fail for several reasons. For example, the photo-exposure process may result in slight misalignment of a patterned reticle or a slight misalignment in a stepped exposure process, where the post exposure photoresist development process may unexpectedly produce unacceptable feature pattern profiles, and so on. Following a photolithographic patterning process, the patterned photoresist layer is subjected to inspection, for example by scanning electron or optical microscopic methods, to assure proper critical dimensions. Photolithographic processes are repeated several times in the course of producing a multi-layer semiconductor device having several device levels. As a result, in a failed photolithographic patterning process, it is critical to be able to salvage the wafer by reworking or re-patterning a second photoresist layer in a reworked photolithographic patterning process.
One problem according to prior art process of reworked photolithographic patterning processes is remaining photoresist residue or damaged areas on the ARC layer surface. For example, prior art processes typically use a dry etching process, referred to as an ashing process, where an oxygen containing plasma is used to remove the photoresist layer. During the etching process, portions of the ARC layer are damaged, causing optical properties including a refractive index and extinction coefficient to be altered, thereby altering the light reflection absorbing properties of the ARC layer. In addition, frequently during the ashing process, photoresist residues are formed that are resistant to the ashing process, leaving residues on the process surface, thereby necessitating an additional wet etching process to remove the residues. As a result, a process cycle is increased and a wafer yield is reduced.
Thus, there is a need in the semiconductor manufacturing art for an improved method for reworking a lithographic process to avoid damage to, and resist residues remaining on, ARC layer surfaces.
It is therefore an object of the invention to provide an improved method for reworking a lithographic process to avoid damage to, and resist residues remaining on, ARC layer surfaces while overcoming other shortcomings and deficiencies of the prior art.